(1) Field of the Invention
The invention relates to an integrated circuit device, and, more particularly, to a method to form a capacitor in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Capacitors are frequently used in integrated circuit devices. Large value capacitors are useful in radio frequency (RF) circuits such as used for filtering or signal processing. Due to trends toward higher levels of integration, it is desirable to integrate large value capacitors onto integrated circuit devices. Various types of integrated capacitors have been devised. In particular, metal-on-metal (MOM) and polysilicon-on-polysilicon (POP) capacitors are formed on integrated circuit devices. In either case, a dielectric layer separates the conductive layers. A particular challenge in the art of integrated circuit manufacture is the formation of large value capacitors. The formation of such capacitors is a key objective of the present invention.
Several prior art inventions relate to integrated circuit capacitors. U.S. Pat. No. 6,383,858 B1 to Gupta et al discloses a method to form an interdigitated capacitor. The method discloses forming metal lines by metal deposition and patterning. U.S. Pat. No. 6,335,557 B1 to Kizilyalli et al and U.S. Pat. No. 6,331,460 B1 to Kizilyalli et al describe a method to form a metal-oxide-metal (MOM) capacitor using metal silicide as a barrier. U.S. Pat. No. 5,880,921 to Tham et al describes a switched capacitor bank using micro electromechanical system (MEMS) technology. U.S. Pat. No. 6,563,191 B1 to Casey et al discloses an interdigitated capacitor structure with a dielectric overlay. The capacitor lines are formed by patterning a deposited conductor layer. U.S. Pat. No. 6,251,740 B1 to Johnson et al teaches a method to form an interdigitated capacitor. U-shaped structures are formed in the underlying dielectric layer. However, chemical mechanical polishing is taught against as a means to pattern the conductive layers for the electrodes.